In various electronic applications, such as radar and communications systems, there is a need to synthesize or generate radio frequency (RF) signals across a wide range of frequencies. Many existing frequency synthesizing techniques, however, are limited by the range of obtainable output frequencies, and/or by excessive noise introduced into the resulting output signals. For example, in analog and digital signal processing operations, frequency dividers are often implemented to generate an output signal of a frequency fout, from an input signal of a frequency fin, where fout=fin/n, wherein “n” is an integer. Likewise, in a traditional regenerative frequency divider, an input signal is mixed with the output of the circuit via a feedback loop. These dividers may achieve very low noise, but are limited to outputs of one-half (½) the input signal frequency (or 1½ times the input frequency). In order to obtain frequency divisions greater than two, multiple frequency dividers may be utilized. For example, these may be arranged in cascade, but with increased complexity, cost, and noise production.
Many applications, however, require production of low-noise frequencies that are not integer multiples of a given input frequency. In these instances, conjugate regenerative dividers, for example, are able to produce fractional division but are complicated to stabilize. Likewise, complementary metal-oxide-semiconductor (CMOS) based dividers produce low noise, but are limited to input frequencies of about 200 MHz. Injection-locked frequency dividers have also been demonstrated at low noise, but have known stability issues with high order divisions.
Alternative systems and methods for providing low-noise frequency generation at fractional division ratios are desired.